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VLSI Chip Design & Computer Architecture Expert Witness
An expert with five decades of experience in electronic and computer engineering, specializing in computer architecture and VLSI chip design. Holds advanced academic credentials including PhD and MSc in Computer Sciences, and is a Life Fellow of IEEE. Extensive expertise includes transistor circuits, logic design, patents, trade secrets, reverse engineering, forensic engineering analysis, source code and performance analysis. Has served as a litigation consultant and expert witness on numerous complex cases involving patents and intellectual property in the computer engineering sector. Familiar with providing forensic analysis, testing, and detailed reports with deposition and trial testimony experience.
Professional Affiliations:
American National Association for Amateur Radio (ARRL), Extra Class
Member of Advisory Board, Silicon Catalyst
Editorial Board, IEEE MICRO
Editorial Board, Journal of VLSI Signal Processing
Publishing Board, Taylor-Francis IEEE Fellow Committee
Associate Editor, IEEE Transactions on Computers
Associate Editor, IEEE Transactions on VLSI
Associate Editor, IEEE Transactions on Circuits and Systems II
Associate Editor, Journal of VLSI Signal Processing
ISSCC Program Committee Member
Program Committee Member for multiple conferences including ASSCC, Low-Power Design, Computer Arithmetic, ICCD, PATMOS track chair
Education:
Ingenieur of Electronics and Telecommunications (BS equivalent)
Dipl. Ingenieur of Electronics and Telecommunication (MSc equivalent)
MSc in Computer Sciences
PhD in Computer Sciences
Areas of expertise:
Cell Phones
Computers
Data Communications
Electronics
Forensic Animation
Information Technology
Intellectual Property
Microelectronics
Semiconductors
Telephony
User Interface
Virtual Reality
Case Study:
Patent Litigation
Trade Secrets Disputes
Reverse Engineering Analysis
Forensic Engineering
Source Code Analysis
Performance Analysis and Testing
Certifications:
IEEE Senior Member
IEEE Fellow
IEEE Life Fellow
